As well known to all, an ordinary memory device reads or writes into an assigned address, but a content addressable memory device is supplied with reference data and outputs information on the existence of data, which is the same as or similar to the reference data, other data stored in a word containing the reference data and the addresses of the data, in addition to function of the ordinary memory device. Accordingly, the content addressable memory device is called an associative memory device also.
The content addressable memory (CAM) is composed of plural CAM cells, and each of the CAM cells is provided with a memory circuit of one bit and a comparator for comparing one bit stored in the memory circuit with a datum of one bit supplied thereto. The comparator circuit is composed of plural N-channel MOSFETs.
In the CAM, since reference is made to the content stored in the memory circuits, the CAM cells constituting the CAM have access to all the address, which is distinct from the RAM having access only to the assigned address. Accordingly, all the signal lines are activated, and high electrical power is consumed.
Hitherto, the content addressable memory device of various kind for reducing consumed electrical power have been proposed. For example, a content addressable memory cell device composed of CAM cells, each of which has a common line serving as both a bit line of a RAM and a reference signal line of a CAM and is provided with a coincidence signal line for outputting the result of comparison and a coincidence detection control signal line for controlling the coincidence signal line, is disclosed in Japanese patent Kokai 2-192098 (a conventional technologyl, hereinafter). Inthis technology, the potential of the coincidence detection control signal line is made to be a low logical level only at the time of the operation of comparison, and thereby the potential of the coincidence signal line is changed into a low logical level from a high logical level at the time of anticoincidence. Since the potential of the coincidence signal line is not made to be a low logical level at the time of write in a RAM operation, the level of the coincidence signal line is unchanged, even in case that N-channel MOSFETs are in anion condition. Accordingly, electrical energy consumed therein is reduced. The content addressable memory device shown the conventional technology 1 is constituted of a parallel connection of the plural CAM cells.
In Japanese patent Kokai 62-293596, a content addressable memory device, which reduces consumption of electrical power at the time of comparison (the conventional technology 2, hereinafter), is disclosed. The content addressable memory device disclosed in the conventional technology 2, in which one word is composed of n bits, comprises a decoder for selecting a word in order to wire a data of n bits, the first CAM cell array, in which one word is composed of m bits, the first sense amplifier for detecting the result of comparison of the fist CAM cell array, the second CAM cell array, which carries out the operation of comparison based on the output of the first sense amplifier, one word of the second CAM cell array being n-m bits, and the second sense amplifier, which detects the result of comparison of the second CAM cell array responding to the output of the first sense amplifier.
In the conventional technology 2, the first CAM cell array is constituted of a parallel connection of them CAM cells, and compares the previously stored data of m bits with the higher m bits of the reference data in bit parallel. Similarly, the second CAM cell array is constituted of a parallel connection of the n-m CAM cells, operates only in case that the output of the first sense amplifier shows coincidence, and compares the previously stored data of n-m bits with the lower n-m bits of the reference data in bit parallel.
In such a structure, the second CAM cell carries out the operation of comparison, after the operation of comparison of the first CAM cell array is completed. Accordingly, the second clock signal is necessary for the operation of comparison of the second CAM cell array, in addition to the first clock signal necessary for the operation of comparison of the first CAM cell array.
Moreover, in a technology disclosed in Japanese patent Kokai 6-89588 (the conventional technology 3, hereinafter), a content addressable memory device, in which a timing control signal for generating a coincidence detection signal is unnecessary, and high speed operation becomes possible by adopting AND logical operation circuits with low electric currents consumed therein, is disclosed. In the conventional technology 3, plural CAM cells are connected in series.
On the aforementioned conventional technologies, problems mention in later are pointed out.
In the conventional technology 1, there is a disadvantage that electrical power consumed at the time of comparison is high. The reason is that in case that the result of comparison shows anticoincidence at the time of comparison, the potential of the coincidence signal line and that of the coincidence detection control signal line, which has nearly the same capacity as that of the coincidence signal line, are changed into low logical levels from high logical levels.
In the content addressable memory device disclosed in the conventional technology 2, clock signals of two kinds, the first and second clock signals, are necessary, and it is difficult to adjust the two clock signals to each other. Moreover, since the CAM cells of both the first and second CAM cell arrays respectively operate in parallel, consumed electrical power becomes high.
In the content addressable memory device disclosed in the conventional technology 3, since the plural CAM cells are connected in series, the speed of operation becomes low, as the number of the CAM cells connected in series increases.